Practice Wire And Reg (3.3.1) - Verilog-Based RTL Design - SOC Design 1: Design & Verification

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6 sample questions

Question 1.
What type of data does a 'wire' in Verilog represent?
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Remember, is it a conduit or a storage?
Question 2.
What is the purpose of 'reg' in Verilog?
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Think about what you want to remember in a circuit.
3Question 3.
What does 'wire' in Verilog do?
- Stores data
- Connects components
- Both
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Is it a storage type or a connector?
4Question 4.
Is 'reg' capable of storing values?
- True
- False
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Think about a type that retains its state.
Question 5.
Design a small Verilog module that includes a wire and a reg. Illustrate how signals flow through the wire while showing how the reg retains state.
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Consider how you would use both types in a single circuit function.
Question 6.
Write a function where changing the value of a reg affects a wire. Demonstrate how the values transition during clock cycles in a simulation.
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Link how changes propagate through the system.

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