Practice Verilog Language Basics (3.2) - Verilog-Based RTL Design

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8 questions

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3 cards from this section. Quick, good the night before a test.
Exercise
6 questions · about 4 min · pass mark 70%. Hints available.
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Quiz
2 questions · about 1 min · pass mark 70%. Hints available.
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6 sample questions

Question 1.
What is a module in Verilog?
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Think of a module as an independent unit in your design.
Question 2.
Name one type of port in Verilog.
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Consider how data enters and exits modules.
3Question 3.
What does a module represent in Verilog?
- Data type
- Building block
- Signal
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Consider the concept of structure in your design.
4Question 4.
True or False: An 'inout' port can only send signals out of a module.
- True
- False
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Think about how it communicates.
Question 5.
Design a Verilog module that combines multiple input types into one output signal. Include at least three inputs and describe how they interact.
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Think about how inputs can logically combine to determine an output.
Question 6.
Create a test module that validates the functionality of the previous combiner module. What signals would you need to apply, and how would you verify the outputs?
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Consider applying both edge cases and typical use cases for thorough validation.

4 more questions in this section. Enroll free to practise them all.