Practice Procedural Blocks (3.5) - Verilog-Based RTL Design - SOC Design 1: Design & Verification

Practice: Procedural Blocks

Lesson 3.5Verilog-Based RTL Design

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10 questions

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3 cards from this section. Quick, good the night before a test.
Exercise
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Quiz
4 questions · about 3 min · pass mark 70%. Hints available.
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6 sample questions

Question 1.
What is the purpose of an always block in Verilog?
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Remember, it runs when certain signals change.
Question 2.
What does the initial block do?
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Think about starting conditions for a game.
3Question 3.
What is an always block primarily used for in Verilog?
- To initialize variables
- To describe constant values
- To model sequential behavior
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Think about what options describe dynamic behavior.
4Question 4.
True or False: Initial blocks can run multiple times during a simulation.
- True
- False
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Consider the role of initial conditions when testing.
Question 5.
Design a simple Verilog module that includes both an always block and an initial block. Explain how the always block implements a counter that increments at every clock cycle.
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Think about how the initial sets a value and how the always block modifies it.
Question 6.
Analyze a provided Verilog code segment with both an always block and initial block. Identify potential errors or improvements, focusing on timing and initialization.
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Check the assignments inside the always block and make sure they align with the intended sequential logic.

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