Practice Basic Testbench Structure (3.7.1) - Verilog-Based RTL Design

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11 questions

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6 questions · about 4 min · pass mark 70%. Hints available.
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6 sample questions

Question 1.
What is the purpose of a testbench in Verilog?
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Think about verification methods.
Question 2.
What signal types would you use for inputs and outputs in a testbench?
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Recall the basic signal types in Verilog.
3Question 3.
What is the main purpose of a testbench in Verilog?
- A) To create the design.
- B) To validate the DUT.
- C) To synthesize the design.
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Think about the verification process.
4Question 4.
True or False: The testbench can be considered a separate module from the DUT.
- True
- False
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Look back at the structure of a testbench.
Question 5.
Create a testbench for a 4-bit adder module. Include clock generation, stimulus for adding numbers, and output monitoring.
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Think about how specific inputs will create the expected output.
Question 6.
Design a testbench that includes error checking for a state machine. Ensure it monitors unexpected states.
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Consider how to define valid states and what unexpected values might be.

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