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2 cards from this section. Quick, good the night before a test.
What is a testbench?
Think about what environment is required for a simulation.
What is the difference between directed and random testbenches?
One is predictable while the other explores unknown scenarios.
What role does a testbench play in RTL simulation?
Think of what it does in a simulation setting.
True or False: Random testbenches are easier to control than directed testbenches.
Which type is based on predefined scenarios?
Design a random testbench in Verilog that generates inputs for a 4-bit adder. Explain your design choices.
Think about how you can utilize Verilog's $random function.
You have a design that uses assertions to maintain a certain condition. Discuss how failing assertions can affect your verification process.
Consider what happens when a condition isn't met during simulation.
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