Practice Assertion-based Verification (6.3.2) - RTL Verification using Simulation Methods

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6 sample questions

Question 1.
Define what an assertion is in the context of verification.
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Think about checks made during simulations.
Question 2.
What does the acronym CAP signify in the context of assertions?
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It relates to the expectation of assertions.
3Question 3.
What is the purpose of assertions in Verilog?
- To generate random input
- To specify design properties that must hold true
- To simulate timing behavior
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Think about what assertions validate.
4Question 4.
True or False: Assertions can only be used in formal verification.
- True
- False
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Consider where assertions are applied.
Question 5.
Create a set of assertions for a simple counter that should never exceed its maximum value.
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Consider the role of the reset and the increment operation.
Question 6.
Discuss how you would implement a formal verification strategy that includes assertions.
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Think about how formal methods apply along with simulation.

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