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2 cards from this section. Quick, good the night before a test.
What is meant by completeness of verification?
Think about what it means to check everything.
Define a counterexample.
It involves demonstrating a failure or incorrect situation.
What does completeness of verification assure?
Consider what completeness guarantees in the context of verification.
True or False: A counterexample is a positive outcome in formal verification.
Counterexamples usually indicate problems rather than confirmations.
Consider a digital circuit designed to prevent overflow in a register. What formal methods might you use to ensure completeness, and what counterexamples could demonstrate possible failures?
Think about what inputs could potentially challenge the design's bounds.
Design a verification strategy for a traffic light controller to ensure all states (green, yellow, red) are correctly handled without any unplanned transitions.
What specific conditions must be verified to prevent unsafe situations?
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