Practice Example: Simple And Gate (2.2.4) - Proficiency in VHDL and Verilog Programming

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9 questions

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6 questions · about 4 min · pass mark 70%. Hints available.
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6 sample questions

Question 1.
What does an entity define in VHDL?
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Consider what connects the internal function to the external environment.
Question 2.
What data type is used for digital signals in the AND gate example?
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Think about what value representations are used.
3Question 3.
What is the function of the entity in a VHDL program?
- Defines the circuit behavior
- Defines inputs/outputs
- Defines the architecture
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Think about what connects internal functions to the outside world.
4Question 4.
True or False: The architecture section is where we specify the type of the signals.
- True
- False
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Recall what each section is responsible for.
Question 5.
Modify the provided VHDL code of the AND gate to implement a 2-input OR gate instead.
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Change the logical operator from AND to OR.
Question 6.
Explain how you would implement a simple NOT gate in VHDL, including both the entity and architecture.
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Recall the role of negation in logical operations.

5 more questions in this section. Enroll free to practise them all.