Practice Tlb Characteristics (14.2.1) - Page Faults - Computer Organisation and Architecture

Practise this section

9 questions

Flashcard drill
3 cards from this section. Quick, good the night before a test.
Exercise
6 questions · about 4 min · pass mark 70%. Hints available.
Sign up to start the exercise
Quiz
3 questions · about 2 min · pass mark 70%. Hints available.
Sign up to start the quiz

6 sample questions

Question 1.
What is a page fault?
Show hintHide hint
Think about what happens when a page is not found in RAM.
Question 2.
What does the valid bit in a page table entry indicate?
Show hintHide hint
Translate 'valid' in terms of memory.
3Question 3.
What happens during a page fault?
- The program aborts immediately
- Data is retrieved from disk
- The virtual address is ignored
Show hintHide hint
Think about what occurs when RAM is insufficient.
4Question 4.
Is the TLB a cache for the page table?
- True
- False
Show hintHide hint
Consider the purpose of a cache.
Question 5.
Given that accessing data from memory typically takes 10 cycles, and a page fault adds 50 cycles for retrieval, calculate the effective time spent retrieving data for 30 instructions where one results in a page fault.
Show hintHide hint
Remember to consider the proportion of hits to misses when calculating cycle time.
Question 6.
Analyze how a fully associative TLB differs from a direct-mapped TLB in terms of cache hit rate for a given workload.
Show hintHide hint
Consider flexibility vs. restriction when thinking about TLB configurations.

5 more questions in this section. Enroll free to practise them all.