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4 cards from this section. Quick, good the night before a test.
What occurs during a page fault?
Think about the relationship between virtual memory and physical memory.
What does a valid bit of 0 signify?
Reflect on how operating systems track memory status.
What action does the OS take during a page fault?
Think about the OS's responsibility.
True or False: A TLB hit occurs when the required address mapping is found.
Contextualize with examples of memory access.
Explain how a system would operate if it experiences a high frequency of page faults. What strategies could be implemented to mitigate this?
Consider the effects of disk latency.
Given an instruction cycle time of 3ms when no page faults occur and 50ms when they do, calculate the effective cycle time for 20 instructions if 3 incur page faults.
Think about the contribution of both hit and miss cycles.
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