Practice Cycles For Tlb Misses (14.2.4) - Page Faults - Computer Organisation and Architecture

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6 sample questions

Question 1.
What does TLB stand for?
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Consider what it does in memory management.
Question 2.
What happens when a page fault occurs?
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Think about where data is stored.
3Question 3.
What is the role of a TLB?
- To store physical addresses
- To cache recent translations of memory addresses
- To manage CPU scheduling
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Think about the role of caches in memory management.
4Question 4.
A TLB miss leads to which of the following?
- True
- False
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What happens when the data isn't found in the TLB?
Question 5.
A process has a TLB hit rate of 90%, and a page fault rate of 10% with an average access time of 20 cycles for hits and 100 cycles for page faults. Calculate the effective access time.
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Use the formula for effective access time, weighing hit and fault rates.
Question 6.
Consider a system with a TLB miss that must service a page fault. If servicing the page fault takes 50 cycles, what happens to the overall access time when this miss occurs every 5 instructions?
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Calculate by averaging total cycles across instructions.

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