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2 cards from this section. Quick, good the night before a test.
What is a page fault?
Consider the definitions related to virtual memory.
How many bits are used in the virtual page number for the FastMATH architecture?
Think about the total address space size.
What is a TLB miss?
Refer to your understanding of TLB functionality.
How many entries does the TLB have in the Intrinsity FastMATH architecture?
Consider the specific architecture details.
If a process encounters 5 page faults out of 100 memory accesses, how does this affect the effective access time if the access time is 50 cycles for a hit and 1000 cycles for a fault?
Break down the total times for hits and faults, then normalize by total accesses.
In a scenario where a TLB hit occurs 90% of the time, if the page hit is 80% of the time, and the cache hit is 70% of the time, calculate the overall expected hit ratio.
Use a cascading probability calculation for combined events.
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