Practice Direct-mapped Caches: Misses, Writes And Performance (4.2) - Direct-mapped Caches: Misses, Writes and Performance

Practice: Direct-mapped Caches: Misses, Writes and Performance

Lesson 4.2Direct-mapped Caches: Misses, Writes and Performance

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8 questions

Flashcard drill
4 cards from this section. Quick, good the night before a test.
Exercise
6 questions · about 4 min · pass mark 70%. Hints available.
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Quiz
2 questions · about 1 min · pass mark 70%. Hints available.
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6 sample questions

Question 1.
What does SRAM stand for?
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Think about the 'S' in SRAM.
Question 2.
What is a cache hit?
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Reflect on what happens during a successful data retrieval.
3Question 3.
What is the access time of SRAM?
- 0.5 to 2.5 nanoseconds
- 50 to 70 nanoseconds
- 5 to 20 milliseconds
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Remember the timing details given for SRAM.
4Question 4.
True or False: A cache miss occurs when requested data is not found in the cache.
- True
- False
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Recall the definition of a cache miss given in class.
Question 5.
Given a cache with 16 lines and a block size of 4 words, calculate the direct mapping for memory block 12.
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Use the mapping function for cache lines.
Question 6.
Create a scenario with four memory accesses: 0, 4, 8, and 12. What will the hit/miss ratio be if they are stored in a direct-mapped cache with 4 lines?
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Visualize the block's mapping to cache lines and identify miss occurrences.

4 more questions in this section. Enroll free to practise them all.