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3 cards from this section. Quick, good the night before a test.
What is a cache hit?
Consider the situation when a data request is successfully met.
Define a cache miss.
Think about what happens when the required data is absent.
What indicates a cache hit?
Think about what happens when the required information is readily accessible.
A cache miss is defined as?
Remember what happens when the cache does not contain the needed address.
A CPU has a memory address of 11100011. The cache has 4 lines, and each block contains 2 bytes. Determine how the address maps to cache.
Break down the bits and apply modulo arithmetic based on the line size.
Design a small direct mapped cache for a hypothetical system: if the main memory has 32 blocks and each block is 8 bytes, how many bits are needed for the cache lines and tags if the cache can hold 8 lines?
Refer back to the organization of cache layout discussed previously.
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