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3 cards from this section. Quick, good the night before a test.
What is gate delay?
Think about the timing of signals at the gates.
Which factor does NOT influence gate delay?
Consider what physical characteristics of the gate would affect speed.
What primarily determines the gate delay in a CMOS circuit?
Consider the factors that change how quickly a charge can move.
Total delay in a CMOS circuit is calculated by summing up which components?
Think about how signals travel from one gate to another.
Calculate the total delay for a circuit with four gates having delays of 1 ns, 3 ns, 2 ns, and 4 ns respectively.
Add all gate delays together.
How would doubling the load capacitance in a circuit influence its timing requirements if initially the delay was 3 ns?
Consider how load capacitance directly affects the rate of signal changes.
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