Practice Formal Verification And Property Checking (9.3.4) - Design Exploration and Automation

Practice: Formal Verification and Property Checking

Lesson 9.3.4Design Exploration and Automation

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9 questions

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4 cards from this section. Quick, good the night before a test.
Exercise
6 questions · about 4 min · pass mark 70%. Hints available.
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Quiz
3 questions · about 2 min · pass mark 70%. Hints available.
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6 sample questions

Question 1.
What is formal verification?
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Think about the purpose of ensuring reliability in VLSI designs.
Question 2.
Define equivalence checking in VLSI design.
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Consider how we compare two representations of a design.
3Question 3.
What is the primary purpose of formal verification?
- To optimize design for performance
- To prove correctness of a design
- To automate design processes
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Remember the primary role of verifying a design's reliability.
4Question 4.
True or False: Liveness properties guarantee the system will not reach a deadlock state.
- True
- False
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Differentiate between properties that avert issues and those that promise outcomes.
Question 5.
Given an RTL design and a gate-level netlist, describe the methods you would use to perform equivalence checking thoroughly.
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Think about different methodologies for comparing outputs.
Question 6.
Create a scenario where a design fails a property check and describe the implications.
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Consider real-world designs where failures could have dire consequences.

5 more questions in this section. Enroll free to practise them all.